DRAMs are comprised of word lines (rows) and bit lines (columns), and bit charge retaining cells adjacent the intersections of the rows and columns. By addressing a row and a column, a memory cell can be read or written to. The present invention concerns the circuitry used to address a column.
Typically a read cycle of the DRAM involves charging a bit line to one-half logic level, dumping the charge stored in a memory cell on the bit line, sensing the charge on the bit line raising it to full logic level and restoring the memory cell, and connecting the bit line carrying full logic level to a data bus. The internal column cycle is usually started by detecting the presence of a stable column address in an address transition detection ATD circuit.